This is a developer’s note about rewriting the Application Programming Interface (API) for the TS-ADC16 and TS-ADC24 PC/104 peripherals. With the existing API being written in 2010 it was decided that a rewrite would be more effective than a comprehensive update. This article will cover the details of the development for the new API and also briefly describe the functions in the API.
Continue reading “Developer Notes on API Rewrite for TS-ADC16 and TS-ADC24”
The TS-ADC24 can provide up to 8 MB/s of ADC data, but the ISA (PC/104) bus on most systems is limited to 2 MB/s bandwidth or less. So one might conclude that the TS-ADC24 is over-designed. However, the TS-ADC24 itself does not require the long ISA strobe times that typical PC/104 systems use, and a well-designed PC/104 system such as the TS-8100-4740 featuring a Spartan 6 FPGA can actually exceed 2MB/s for sustained bursts. This translates into sampling 4 ADC channels at 250 kHz or even 500 kHz. This is possible due to standard functionality in the FPGA including customizable bus timing, user DMA, and an embedded processor. With extra engineering, 1000 kHz would be possible, but this article explores what can be accomplished by a typical C programmer who does not want to venture into the realm of FPGA development.
Continue reading “Improving PC/104 Bandwidth using FPGA Microcontroller”
